Microelectronic elements, such as semiconductor chips, are typically incorporated in a microelectronic package having terminals for forming electrical connections between the semiconductor chip and a second microelectronic element. Methods of making a microelectronic package typically include assembling the semiconductor chip with a microelectronic component. The microelectronic component incorporates conductive features for connecting with contacts on the semiconductor chip and for connecting with the second microelectronic element.
The microelectronic component may comprise a dielectric layer including conductive features on both of the two major surfaces of the dielectric layer. Vias, which comprise holes that extend from one major surface to another major surface of the dielectric layer, are typically used to form electrical connections between features on each major surface.
After a via is formed in a dielectric layer, the vias are bounded by walls of the dielectric layer. The vias are lined with an electrically conductive material so that the conductive features on one major surface are electrically connected to conductive features on the other major surface. To line the vias with conductive material, the vias are first “seeded” by lining the vias with a small amount of electrically conductive material so as to cover the dielectric walls of the via. Additional electrically conductive material can then be electroplated onto the seeded vias. After the vias are lined, terminals for connecting to the second microelectronic element are formed in contact with the vias. Lining the vias by seeding the vias and then electroplating conductive material in the vias is time consuming and expensive.
Components having conductive features on two sides, or “two metal components,” are typically made by forming conductive features on one side of the component separately from the conductive features on the other side of the component. A two metal component may be formed from a dielectric layer having a layer of metal on each of the major surfaces of the dielectric layer. Photolithographic techniques are used to form the conductive features on both sides of the dielectric layer. The conductive features on one side of the dielectric layer are formed before the vias are formed. After vias are formed, the vias are lined and then the conductive features on the other side of the dielectric layer are formed. Multiple steps are required in forming the conductive features from the top metal layer, forming and lining the vias, and forming conductive features from the bottom metal layer separately.
Further improvements in forming microelectronic components and microelectronic packages are desired.